The present invention relates to a semiconductor memory device of high integration density.
A conventional dynamic ram access memory (DRAM) has high integration density and has memory cells, each of which consists of a switching transistor and a capacitor. The physical structure of such a DRAM memory cell is shown in FIG. 2A, while FIG. 2B is a schematic diagram of the same. In each case, one bit of a memory cell is shown, which would be one memory cell of a memory matrix having a plurality of memory cells. The switching transistor is a MOSFET Q. The capacitor electrode CE stores data and is in the form of an impurity conductivity type opposed to that of the substrates and electrically separated by a PN junction between the electrode CE and the substrate semiconductor S. The capacitor electrode CE is electrically connected to the diffusion electrode layer of the switching transistor Q, the gate of which, G, is connected to word line 200 on the matrix. Therefore, the drain or source is formed by the capacitor electrode CE and the other of the source or drain is connected to the bit line 850 of the matrix. When the switching transistor is turned off, the capacitor electrode CE can store data because it is electrically separated from peripheral electrodes.
In the conventional structure of FIG. 2, the stored charge on the capacitor electrode CE is decreased as time elapses because of leakage through the junction with the substrate S and also because of the leakage current of the switching transistor Q. Therefore, the capacitor electrode CE cannot hold data permanently or statically. Thus, it is necessary to execute a "refresh" for rewriting data at frequent intervals. Because the refresh interval is determined by the stored charge amount, it is necessary to increase the stored charge amount in order to decrease the refresh frequency. However, because the stored charge amount of a capacitor is proportional to the area of the capacitor, there is a big problem that the stored charge amount decreases as the integration density of a memory cell increases, which increase in integration density decreases the capacitor size and correspondingly disadvantageously increases the frequency of refresh.
Moreover, when the size of the switching MOSFET is decreased, the leakage current flowing in the diffusion layer between source and drain usually increases, which is known as the short channel effect. Therefore, when integration density increases, the leakage current correspondingly increases to correspondingly increase the refresh frequency, because it is difficult to hold the off state due to such leakage causing the stored charge amount to decrease.